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High performance bipolar FPLAsTAKEDA, T; MATSUHIRO, K; SUZUKI, M et al.Review of the electrical communication laboratories. 1983, Vol 31, Num 4, pp 566-575, issn 0029-067XArticle

Sur la vérification complète des matrices logiques programmables. INOVIKOV, YA. A.Avtomatika i telemehanika. 1984, Num 6, pp 146-153, issn 0005-2310Article

Sur la vérification complète des matrices logiques programmables. IINOVIKOV, YA. A.Avtomatika i telemehanika. 1984, Num 7, pp 137-146, issn 0005-2310Article

A new concept for supermodular alignment networkPARANJPE, S. K; EKTARE, A. B; MITAL, D. P et al.International journal of electronics. 1984, Vol 56, Num 6, pp 815-822, issn 0020-7217Article

Quasi-static adiabatic logic 2N-2N2P2D familyHE, Y; TIAN, J; TAN, X et al.Electronics Letters. 2006, Vol 42, Num 16, pp 905-907, issn 0013-5194, 3 p.Article

Programmable logic machine (a programmable cell array)SKOKAN, Z. E.IEEE journal of solid-state circuits. 1983, Vol 18, Num 5, pp 572-578, issn 0018-9200Article

IUMRS-ICEM-2010. Materials and Devices for Future Logic TechnologyCHOI, Rino; CHEOL SEONG HWANG; YOUNG-BAE PARK et al.Microelectronic engineering. 2012, Vol 89, issn 0167-9317, 143 p.Conference Proceedings

Multi-valued logic systemsHAWKEN, R. E.International journal of electronics. 1989, Vol 67, Num 5, issn 0020-7217, 142 p.Serial Issue

Application of AlGaAs/GaAs HBT's to high-speed CML logic family fabricationMOHAMMAD MADIHIAN; TANAKA, S.-I; HAYAMA, N et al.I.E.E.E. transactions on electron devices. 1989, Vol 36, Num 4, pp 625-631, issn 0018-9383, 7 p.Article

On the approach of the stationary state in Kauffman's random Boolean networkHILHORST, H. J; NIJMEIJER, M.Journal de physique (Paris). 1987, Vol 48, Num 2, pp 185-191, issn 0302-0738Article

I2LII.COOK B; MCNALLY SH; AUNG SAN et al.1975; IN: INT. ELECTRON DEVICES MEET.; WASHINGTON, D.C.; 1975; NEW YORK; INST. ELECTR. ELECTRON. ENG.; DA. 1975; PP. 284-287; BIBL. 4 REF.; ART. ANGL.Conference Paper

VERTICAL INJECTION LOGIC.NAKANO T; HORIBA Y; YASUOKA A et al.1975; IN: INT. ELECTRON DEVICES MEET.; WASHINGTON, D.C.; 1975; NEW YORK; INST. ELECTR. ELECTRON. ENG.; DA. 1975; PP. 555-558; BIBL. 4 REF.Conference Paper

Variable threshold logic ― a highly flexible logicKIM, C; KUSHIYAMA, N; SHONO, K et al.IEEE electron device letters. 1985, Vol 6, Num 7, pp 390-393, issn 0741-3106Article

Eléments logiques pour les systèmes à structure variableGOLIK, L. L; ELINSON, M. I; PEROV, N. I et al.Mikroèlektronika (Moskva). 1984, Vol 13, Num 3, pp 206-213, issn 0544-1269Article

Modélisation de circuits logiques élémentaires à effet Josephson = Modelling of elementary logic Josephson effect circuitsMATHERON, G; MAS, P; MIGNY, P et al.1982, 43 p.Report

FIELD PROGRAMMABLE LOGIC DEVICESLARSON TL; DOWNEY C.1980; ELECTRON. ENG.; ISSN 0013-4902; GBR; DA. 1980; VOL. 52; NO 633; PP. 37-54; (10 P.); BIBL. 7 REF.Article

A new architecture for designing noise-tolerant digital circuitsLAKES, Jeremy M; LEE, Samuel C.Proceedings of SPIE, the International Society for Optical Engineering. 2011, Vol 7980, issn 0277-786X, isbn 978-0-8194-8542-7, 79800J.1-79800J.7Conference Paper

Multilevel logical networksKARPOVSKY, M.IEEE transactions on computers. 1987, Vol 36, Num 2, pp 215-226, issn 0018-9340Article

An algorithm for the partitioning of logic circuitsROBERTS, M. W; LALA, P. K.IEE proceedings. Part E. Computers and digital techniques. 1984, Vol 131, Num 4, pp 113-118, issn 0143-7062Article

Hard magnetic cylindrical domains (HMD) as elements of multistate logicSZKODNY, T.Bulletin of the Polish Academy of Sciences. Technical sciences. 1984, Vol 32, Num 5-6, pp 333-339, issn 0239-7528Article

Multiple constrained folding of programmable logic arrays: theory and applicationsDE MICHELI, G; SANGIOVANNI-VINCENTELLI, A.IEEE transactions on computer-aided design of integrated circuits and systems. 1983, Vol 2, Num 3, pp 151-167, issn 0278-0070Article

ATILA, a program to generate test patterns for scan testable logicSMITH, P. J.GEC journal of research. 1988, Vol 6, Num 3, pp 147-151, issn 0264-9187Article

Development of a user friendly gate-level logic simulatorSTIGALL, P. D; KUMAR SHIV.Computers & electrical engineering. 1987, Vol 13, Num 3-4, pp 147-167, issn 0045-7906Article

Evaluating the signal-reliability of logic circuitsKYUNG-SHIK KOH.IEEE transactions on reliability. 1985, Vol 34, Num 3, pp 233-235, issn 0018-9529Article

Optimal shut-down logic for protective systemsKOHDA, T; KUMAMOTO, H; INOUE, K et al.IEEE transactions on reliability. 1983, Vol 32, Num 1, pp 26-29, issn 0018-9529Article

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